Intel D15343-003 User Manual
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D15343-003
Intel
®
82854 Graphics Memory Controller Hub (GMCH)
SVID – Subsystem Vendor Identification Register ................................................ 55
4.8.10 SID – Subsystem Identification Register ............................................................... 56
4.8.11 CAPPTR – Capabilities Pointer Register............................................................... 56
4.8.12 CAPID – Capabilities Identification Register (Device #0) ...................................... 57
4.8.13 GMC – GMCH Miscellaneous Control Register (Device #0) ................................. 58
4.8.14 GGC – GMCH Graphics Control Register (Device #0).......................................... 59
4.8.15 DAFC – Device and Function Control Register (Device #0).................................. 60
4.8.16 FDHC – Fixed DRAM Hold Control Register (Device #0)...................................... 60
4.8.17 PAM(6:0) – Programmable Attribute Map Register (Device #0)............................ 61
4.8.18 SMRAM – System Management RAM Control Register (Device #0) .................... 64
4.8.19 ESMRAMC – Extended System Management RAM Control (Device #0) ............. 65
4.8.20 ERRSTS – Error Status Register (Device #0) ....................................................... 66
4.8.21 ERRCMD – Error Command Register (Device #0)................................................ 67
4.8.22 SMICMD – SMI Error Command Register (Device #0) ......................................... 68
4.8.23 SCICMD – SCI Error Command Register (Device #0) .......................................... 69
4.8.24 SHIC – Secondary Host Interface Control Register (Device #0) ........................... 70
4.8.25 HEM – Host Error Control, Status, and Observation (Device #0).......................... 71
Intel 854 GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function
SVID – Subsystem Vendor Identification Register ................................................ 77
4.9.10 SID – Subsystem Identification Register ............................................................... 77
4.9.11 CAPPTR – Capabilities Pointer Register............................................................... 78
4.9.12 DRB – DRAM Row (0:3) Boundary Register (Device #0)...................................... 78
4.9.13 DRA – DRAM Row Attribute Register (Device #0) ................................................ 79
4.9.14 DRT – DRAM Timing Register (Device #0) ........................................................... 80
4.9.15 PWRMG – DRAM Controller Power Management Control Register (Device #0).. 83
4.9.16 DRC – DRAM Controller Mode Register (Device #0) ............................................ 85
4.9.17 DTC – DRAM Throttling Control Register (Device #0) .......................................... 88
4.10.1 VID – Vendor Identification Register...................................................................... 92
4.10.2 DID – Device Identification Register ...................................................................... 93
4.10.3 PCICMD – PCI Command Register....................................................................... 94
4.10.4 PCISTS – PCI Status Register .............................................................................. 95
4.10.5 RID – Revision Identification Register ................................................................... 96
4.10.6 SUBC – Sub-Class Code Register ........................................................................ 96
4.10.7 BCC – Base Class Code Register ......................................................................... 96
4.10.8 HDR – Header Type Register................................................................................ 97