IBM DS8000 - Manual (Page 284)

262 DS8000 Series: Concepts and Architecture
Figure 12-6 Standard pSeries POWER5 p570 2-way SMP processor complexes for DS8100-921
Figure 12-7 provides a less abstract view and outlines some details on the dual 2-way
processor complex of a DS8100-921, its gates to host servers through HAs, and its
connections to the disk storage back end through the DAs.
Figure 12-7 DS8100-921 with four I/O enclosures
Each of the two processor complexes is interconnected through the pSeries-based RIO-G
interconnect technology and includes up to four I/O enclosures which equally communicate to
either processor complex. Note that there is some affinity between the disk subsystem and its
individual ranks to either the left processor complex, server 0, or to the right processor
Adapter Adapter
Adapter Adapter
To host
servers
S
to
rag
e server
RIO-G Module
POWER5 2-way SMP
Processor
Processor
L1,2
Memory
L1,2
Memory
Memory
L3
Memory
Processor Processor
HA
DA
RIO-G Module
RIO-G Module
PowerPC
Fibre Channel
Protocol Proc Fibre Channel
Protocol Proc
RIO-G Interconnect
I/O enclosure
4 HAs
DA
PowerPC
Fibre Channel
Protocol Proc Fibre Channel
Protocol Proc
2 Gbps Fibre Channel ports
2 Gbps Fibre Channel ports
POWER5 2-way SMP
Memory
L3
Memory
RIO-G Module
Processor
Processor
L1,2
Memory
L1,2
Memory
Server 1
RIO-G Module
POWER5 2-way SMP
Processor Memory
Processor
L1,2
Memory
L3
Memory
L1,2
Memory
Server 0