Motorola MVME2400 - Manual (Page 39)

Installing the MVME240x Hardware
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8. Replace the chassis or system cover(s), cable peripherals to the
panel connectors as appropriate, reconnect the system to the AC or
DC power source, and turn the equipment power on.
9. The MVME240x’s green CPU LED indicates activity as a set of
confidence tests is run, and the debugger prompt PPC1-Bug>
appears.
Installation Considerations
The MVME240x draws power from the VMEbus backplane connectors P1
and P2. P2 is also used for the upper 16 bits of data in 32-bit transfers, and
for the upper 8 address lines in extended addressing mode. The
MVME240x may not function properly without its main board connected
to VMEbus backplane connectors P1 and P2.
Whether the MVME240x operates as a VMEbus master or as a VMEbus
slave, it is configured for 32 bits of address and 32 bits of data (A32/D32).
However, it handles A16 or A24 devices in the address ranges indicated in
Chapter 4. D8 and/or D16 devices in the system must be handled by the
PowerPC processor software. Refer to the memory maps in Chapter 4.
The MVME240x contains shared onboard DRAM whose base address is
software-selectable. Both the onboard processor and off-board VMEbus
devices see this local DRAM at base physical address $00000000, as
programmed by the PPCBug firmware. This may be changed via software
to any other base address. Refer to the MVME240x programmer's
reference guide for more information.
If the MVME240x tries to access off-board resources in a nonexistent
location and is not system controller, and if the system does not have a
global bus timeout, the MVME240x waits forever for the VMEbus cycle
to complete. This will cause the system to lock up. There is only one
situation in which the system might lack this global bus timeout: when the
MVME240x is not the system controller and there is no global bus timeout
elsewhere in the system.
Multiple MVME240x boards may be installed in a single VME chassis.
Each must have a unique Universe address, selected by setting jumpers on
its J17 header, as described in Preparing the MVME240x. In general,
hardware multiprocessor features are supported.