SMSC LAN9420 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for LAN9420 SMSC
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 169 |
| Size: | 1.65 MB |
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Document Outline
- Chapter 1 Introduction
- Chapter 2 Pin Description and Configuration
- Chapter 3 Functional Description
- 3.1 Functional Overview
- 3.2 PCI Bridge (PCIB)
- 3.3 System Control Block (SCB)
- 3.3.1 Interrupt Controller
- 3.3.2 Wake Event Detection Logic
- 3.3.3 General Purpose Timer (GPT)
- 3.3.4 Free-Run Counter (FRC)
- 3.3.5 EEPROM Controller (EPC)
- Table 3.2 EEPROM Format
- Table 3.3 EEPROM Variable Defaults
- Figure 3.7 EEPROM Access Flow Diagram
- Figure 3.8 EEPROM ERASE Cycle
- Figure 3.9 EEPROM ERAL Cycle
- Figure 3.10 EEPROM EWDS Cycle
- Figure 3.11 EEPROM EWEN Cycle
- Figure 3.12 EEPROM READ Cycle
- Figure 3.13 EEPROM WRITE Cycle
- Figure 3.14 EEPROM WRAL Cycle
- Table 3.4 Required EECLK Cycles
- 3.3.6 System Control and Status Registers (SCSR)
- 3.4 DMA Controller (DMAC)
- 3.4.1 DMA Controller Architecture
- 3.4.2 Data Descriptors and Buffers
- Figure 3.15 Ring and Chain Descriptor Structures
- Figure 3.16 Receive Descriptor
- Table 3.5 RDES0 Bit Fields
- Table 3.6 RDES1 Bit Fields
- Table 3.7 RDES2 Bit Fields
- Table 3.8 RDES3 Bit Fields
- Figure 3.17 Transmit Descriptor
- Table 3.9 TDES0 Bit Fields
- Table 3.10 TDES1 Bit Fields
- Table 3.11 TDES2 Bit Fields
- Table 3.12 TDES3 Bit Fields
- 3.4.3 Initialization
- 3.4.4 Transmit Operation
- 3.4.5 Receive Operation
- 3.4.6 Receive Descriptor Acquisition
- 3.4.7 Suspend State Behavior
- 3.4.8 Stopping Transmission and Reception
- 3.4.9 TX Buffer Fragmentation Rules
- 3.4.10 DMAC Interrupts
- 3.4.11 DMAC Control and Status Registers (DCSR)
- 3.5 10/100 Ethernet MAC
- 3.6 10/100 Ethernet PHY
- 3.7 Power Management
- Chapter 4 Register Descriptions
- Figure 4.1 LAN9420/LAN9420i CSR Memory Map
- 4.1 Register Nomenclature
- 4.2 System Control and Status Registers (SCSR)
- Table 4.2 System Control and Status Register Addresses
- 4.2.1 ID and Revision (ID_REV)
- 4.2.2 Interrupt Control Register (INT_CTL)
- 4.2.3 Interrupt Status Register (INT_STS)
- 4.2.4 Interrupt Configuration Register (INT_CFG)
- 4.2.5 General Purpose Input/Output Configuration Register (GPIO_CFG)
- 4.2.6 General Purpose Timer Configuration Register (GPT_CFG)
- 4.2.7 General Purpose Timer Current Count Register (GPT_CNT)
- 4.2.8 Bus Master Bridge Configuration Register (BUS_CFG)
- 4.2.9 Power Management Control Register (PMT_CTRL)
- 4.2.10 Free Run Counter (FREE_RUN)
- 4.2.11 EEPROM Command Register (E2P_CMD)
- 4.2.12 EEPROM Data Register (E2P_DATA)
- 4.3 DMAC Control and Status Registers (DCSR)
- Table 4.4 DMAC Control and Status Register (DCSR) Map
- 4.3.1 Bus Mode Register (BUS_MODE)
- 4.3.2 Transmit Poll Demand Register (TX_POLL_DEMAND)
- 4.3.3 Receive Poll Demand Register (RX_POLL_DEMAND)
- 4.3.4 Receive List Base Address Register (RX_BASE_ADDR)
- 4.3.5 Transmit List Base Address Register (TX_BASE_ADDR)
- 4.3.6 DMA Controller Status Register (DMAC_STATUS)
- 4.3.7 DMA Controller Control (Operation Mode) Register (DMAC_CONTROL)
- 4.3.8 DMA Controller Interrupt Enable Register (DMAC_INTR_ENA)
- 4.3.9 Missed Frame and Buffer Overflow Counter Reg (MISS_FRAME_CNTR)
- 4.3.10 Current Transmit Buffer Address Register (TX_BUFF_ADDR)
- 4.3.11 Current Receive Buffer Address Register (RX_BUFF_ADDR)
- 4.4 MAC Control and Status Registers (MCSR)
- Table 4.5 MAC Control and Status Register (MCSR) Map
- 4.4.1 MAC Control Register (MAC_CR)
- 4.4.2 MAC Address High Register (ADDRH)
- 4.4.3 MAC Address Low Register (ADDRL)
- 4.4.4 Multicast Hash Table High Register (HASHH)
- 4.4.5 Multicast Hash Table Low Register (HASHL)
- 4.4.6 MII Access Register (MII_ACCESS)
- 4.4.7 MII Data Register (MII_DATA)
- 4.4.8 Flow Control Register (FLOW)
- 4.4.9 VLAN1 Tag Register (VLAN1)
- 4.4.10 VLAN2 Tag Register (VLAN2)
- 4.4.11 Wakeup Frame Filter (WUFF)
- 4.4.12 Wakeup Control and Status Register (WUCSR)
- 4.4.13 Checksum Offload Engine Control Register (COE_CR)
- 4.5 PHY Registers
- Table 4.7 PHY Control and Status Registers
- 4.5.1 Basic Control Register
- 4.5.2 Basic Status Register
- 4.5.3 PHY Identifier 1
- 4.5.4 PHY Identifier 2
- 4.5.5 Auto Negotiation Advertisement
- 4.5.6 Auto Negotiation Link Partner Ability
- 4.5.7 Auto Negotiation Expansion
- 4.5.8 Mode Control/Status
- 4.5.9 Special Modes
- 4.5.10 Special Control/Status Indications
- 4.5.11 Interrupt Source Flag
- 4.5.12 Interrupt Mask
- 4.5.13 PHY Special Control/Status
- 4.6 PCI Configuration Space CSR (CONFIG CSR)
- Chapter 5 Operational Characteristics
- 5.1 Absolute Maximum Ratings*
- 5.2 Operating Conditions**
- 5.3 Power Consumption
- 5.4 DC Specifications
- 5.5 AC Specifications
- 5.6 PCI Clock Timing
- 5.7 PCI I/O Timing
- 5.8 EEPROM Timing
- 5.9 Clock Circuit
- Chapter 6 Package Outline
- Chapter 7 Revision History