HP PAVILION NX9005 - Manual (Page 118)

Service Manual Troubleshooting and Diagnostics 3-21
Beep Codes POST Description
1-2-1-4 Initialize PCI Bus Mastering devices
1-2-2-1 Initialize keyboard controller
1-2-2-3 BIOS ROM checksum
1-2-2-4 Initialize cache before memory Auto size
1-2-3-1 8254 timer initialization
1-2-3-3 8237 DMA controller initialization
1-2-4-1 Reset Programmable Interrupt Controller
1-3-1-1 Test DRAM refresh
1-3-1-3 Test 8742 Keyboard Controller (on motherboard)
1-3-2-1 Set ES segment register to 4 GB
1-3-3-1 Auto size DRAM; or wrong type or no RAM installed
1-3-3-2 Initialize POST Memory Manager
1-3-3-3 Clear 512 KB base RAM
1-3-4-1 RAM failure on address line xxxx
1-3-4-3 RAM failure on data bits xxxx of low byte of memory bus
1-3-4-4 Enable cache before system BIOS shadow
1-4-1-1 RAM failure on data bits xxxx of high byte of memory bus
1-4-1-3 Test CPU bus-clock frequency
1-4-1-4 Initialize Phoenix Dispatch Manager
1-4-2-3 Warm start shut down
1-4-3-1 Shadow system BIOS ROM
1-4-3-3 Auto size cache
1-4-4-1 Advanced configuration of chipset registers
1-4-4-2 Load alternate registers with CMOS values
2-1-1-2 Initialize extended memory for ROMPilot
2-1-1-3 Initialize interrupt vectors
2-1-2-2 POST device initialization
2-1-2-3 Check ROM copyright notice
2-1-2-4 Initialize I20 support
2-1-3-1 Check video configuration against CMOS
2-1-3-2 Initialize PCI bus and devices
2-1-3-3 Initialize all video adapters in system
2-1-3-4 QuietBoot start (optional)
2-1-4-1 Shadow video BIOS ROM
2-1-4-3 Display BIOS copyright notice
2-1-4-4 Initialize MultiBoot
2-2-1-1 Display CPU type and speed
2-2-1-2 Initialize EISA board
2-2-1-3 Test keyboard
2-2-2-1 Set key Select if enabled
2-2-2-2 Enable USB devices
2-2-3-1 Test for unexpected interrupts
2-2-3-2 Initialize POST display service
2-2-3-3 Display prompt "Press F2 to enter SETUP"
2-2-3-4 Disable CPU cache
2-2-4-1 Test RAM between 512 and 640 KB
2-3-1-1 Test extended memory
2-3-1-3 Test extended memory address lines
2-3-2-1 Jump to UserPatch1
2-3-2-3 Configure advanced cache registers