Sundance SMT351 - Manual (Page 9)

Version 1.6 Page 9 of 25 SMT351 User Manual
Block description
This section describes the major blocks of the SMT351 board.
FPGA
The SMT351 board uses a Xilinx Virtex II Pro (XC2VP7, XC2VP20 or XC2VP30) to
control the data flow between the SMT351 board and external devices. The FPGA is
also used to implement the SHB, comport and DDR SDRAM interfaces.
The FPGA is configured via a 6-pin JTAG header or from a user-selectable Comport.
Memory
The SMT351 board contains sixteen 133 MHz DDR SDRAM components (from
Micron or Samsung) that provide up to 1 GB of storage capacity.
The DDR SDRAM is a high-speed CMOS, dynamic random-access memory.
Two versions of the SMT351 exist:
• SMT351-M: provides 512MB storage capability;
• SMT351-G: provides 1GB storage capability.
CPLD
A Xilinx CPLD is used to manage configuring the FPGA. It connects to the six
comports available on the module.
Sundance High Speed Bus
Two SHB connectors are available on the SMT351.
Unidirectional 32-bit SHB interfaces are implemented on SHB connectors. They run
at 100 MHz, giving a 400MB/s data rate thru the SMT351.
SHB A implements a receiver-only interface while SHB B implements a transmitter-
only interface.
Please refer to the SUNDANCE SHB specification for more details.
Comports
The SMT351 provides up to 6 comports, which are used to receive the configuration
bitstream and commands to the FPGA. Once configured, the SMT351 is controlled
via comport 3.
The number of comports provided depends on the type of FPGA fitted on the board:
• XC2VP7 provides 3 comports: 0, 1 and 3.
• XC2VP20 or XC2VP30s provides 6 comports.