Sundance SMT351 - Manual (Page 17)

Version 1.6 Page 17 of 25 SMT351 User Manual
Clock structure
This section describes the various clock domains in the FPGA.
The figure below shows the four clock domains of the SMT351 design and their
interrelation.
SHB
A
SHB
B
Memory
compartment 0
Memory
compartment 1
Mux
400
MBytes/
sec
400
MBytes/
sec
Registers
Com
Port
Control
words
Input
buffer
Output
buffer
Input clock
domain
DDR SDRAM
clock domain
Output clock
domain
Figure 5: FPGA’s clock domains
Table 4: FPGA’s clock domains description
Clock domain Colour Frequency Description
ComPort 50 MHz Comport and registers clock
Data input
≤ 100 MHz
SHB A clock.
Data output 100 MHz SHB B clock.
DDR SDRAM 100 MHz DDR SDRAM clock.