Jp2 pinout, Figure 7: ttl i/os (jp2) pinout, Jp2: ttl i/os – Sundance SMT351 User Manual
Page 23: The following diagram shows jp2’s pinout
Version 1.6
Page 23 of 25
SMT351 User Manual
JP2 pinout
The following diagram shows JP2’s pinout:
2
TTL
0
4
TTL
2
6
GND
1
VCC
3
TTL
1
5
TTL
3
JP2: TTL I/Os
Figure 7: TTL I/Os (JP2) pinout
A square is drawn around pin 1 on PCB to indicate its location (Represented on
figure 5 in connectors location section).
The following table shows JP2 mapping to the FPGA:
Signal name
FPGA pin
number
TTL0 AC10
TTL1 AD10
TTL2 AC11
TTL3 AD11
See also other documents in the category Sundance Equipment:
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- SMT6035 v.2.2 (39 pages)
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