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Measurement Computing STLITE-CPCI-xxx User Manual

Page 18

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14

GPIO IN Register (0x67 offset of PCI Header) Read Only

D7

D6

D5

D4

D3

D2

D1

D0

X

SDO

X

X

RESERVED

RESERVED

RESERVED

RESERVED

GPIO3

GPIO2

GPIO1

GPIO0

This register provides read-back capability for the serial data (SDO) from any one of the three A/D converters
used to measure slot temperature, power supply voltages or fan current.

The lower nibble (bits 0-3) is reserved by the 21150 bridge chip. Reading from this part of the register will
return all zeros.

NOTE: When reading the upper nibble (bits 4-7), be sure to mask off unwanted bits to avoid incorrect data
being returned.

GPIO CNTRL Register (0x66 offset of PCI Header)

Read/Write

D7

D6

D5

D4

D3

D2

D1

D0

GPIO3_BI

GPIO2_BI

GPIO1_BI

GPIO0_BI

GPIO3_IN

GPIO2_IN

GPIO1_IN

GPIO0_IN

This register configures each of the Expansion card’s GPIO bits as either bi-directional or input type.

Bits 0-3 of this register operate in a “Write-1-To-Clear” manner. Writing a “1” to any bit in the lower nibble
will configure the corresponding GPIO bit as input type.

Bits 4-7 of this register operate as “Write-1-To-Set.” Writing a “1” to any bit in the upper nibble will configure
the corresponding GPIO bit as bi-directional.

Writing the value “0” to this register has no effect. Reading from this register returns the last value poked in.

7.3

SATELLITE HOST BOARD 21150 BRIDGE REGISTERS

GPIO OUT Register ( 0x65 offset of PCI Header )

Read/Write

7

6

5

4

3

2

1

0

X

X

WD_ON

X

X

X

WD_OFF

X

GPIO3

GPIO2

GPIO1

GPIO0

GPIO3

GPIO2

GPIO1

GPIO0

This register is used to control the user-configurable watchdog timer circuit located on the Expansion board.

Writing a “1” to the WD_OFF bit of the lower nibble will disable the Watchdog Timer.

Writing a “1” to the WD_ON bit in the upper nibble will turn the Watchdog Timer on.

Writing the value “0” to this register has no effect, while reading from this register will return the last value
poked in.

GPIO CNTRL Register (0x66 offset of PCI Header)

Read/Write

D7

D6

D5

D4

D3

D2

D1

D0

GPIO3_BI

GPIO2_BI

GPIO1_BI

GPIO0_BI

GPIO3_IN

GPIO2_IN

GPIO1_IN

GPIO0_IN

This register configures each of the PCI Host card GPIO bits as either bi-directional or input type.

Bits 0-3 of this register operate in a “Write-1-To-Clear” manner. Writing a “1” to any bit in the lower nibble
will configure the corresponding GPIO bit as input type.

Bits 4-7 of this register operate as “Write-1-To-Set.” Writing a “1” to any bit in the upper nibble will configure
the corresponding GPIO bit as bi-directional.

Writing the value “0” to this register has no effect. Reading from this register returns the last value poked in.