Measurement Computing STLITE-CPCI-xxx User Manual
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5.4
EXTENDED DAISY CHAIN CONFIGURATION
If, rather than attaching the third expansion chassis to Bus 2, we had attached it to Bus 6 (in the second
expansion rack), then the first motherboard bus in the 3
rd
rack would be further downstream (logically speaking)
than Bus 4. (Actually, if attaching to Bus 6 in the 2
nd
rack, the first bus in the 3rd will be Bus 8.)
All of this not withstanding, bus numbering is determined by the algorithm implemented by your BIOS or
console firmware configuration code. The labeling shown in the prior examples assumes:
1.
The BIOS or firmware runs a true “depth-first” search on the PCI bus hierarchy.
2.
Your BIOS or firmware will actually deal with multiple PPBs.
5.5
CPCI CARD CONFLICTS
If it appears that a CPCI card is interfering with the operation of another, try reorganizing the card layout on the
motherboard. Sometimes, changing the order that the BIOS or firmware configures the cards will resolve
conflict issues.
5.6
BIOS/FIRMWARE REQUIREMENTS
System manufacturers use various names for their console firmware. For example, IBM-PC-compatible
firmware is called BIOS code. SUN or MAC computers call it “Open Firmware” code. DEC Alpha computers
running UNIX have “SRM Console Code” but on Digital computers running Windows NT, its referred to as
“ARC Console Code” or “Alpha BIOS.
Naming conventions aside, the firmware performs the same functions. It must contain a set of hardware-specific
routines that are called during the early phases of a start-up. These callable routines recognize the PCI hardware
and configure the system architecture for use.
The PCI BIOS specification is the part of the PCI Local Bus Specification that deals with this class of code. A
similar standard for non-WinTel systems is IEEE 1275-1994 Open Firmware Bus Binding Specification. These
standards provide a consistent architecture for PCI option identification and configuration during a system boot-
up.
During boot-up, the CPCI bus is probed to determine what cards are present. The probe instructions determine
which slots contain valid cards and which are unused. The configuration code should be able to look at up to
255 PCI/CPCI buses, detect all installed cards, and perform all configuration processing for each PCI/CPCI
card.
In order to configure all installed CPCI cards in an expanded system, the console firmware must be able to
traverse multiple levels of bridges. While 255 is the theoretical limit, the actual limit is lower but still should be
100 or more.
Typically the firmware or BIOS code accommodates multiple bridges (and PCI buses). However, some older
systems place a limit on the number of bridges that can be configured during a start-up. Your firmware must be
able to address at least two levels of PCI-to PCI bridges in order to use an 8-slot CPCI Expansion Chassis. A 16-
slot CPCI expansion system would require four bridge levels.
For daisy-chained or fanned-out systems, count all the bridge levels to the most deeply nested PCI bus to
determine the number of bridge levels that must be traversed.
If you are experiencing problems with installation and detection of multiple bridges or multiple PCI boards,
refer to the Satellite Systems link on the Measurement Computing website (
www.measurementcomputing.com
).