Measurement Computing PC-CARD-DAS16/330 - Manual (Page 18)

PC-CARD-DAS16/330 User's Guide Functional Details
Input range vs. speed
The design of the analog front end is critical to maintaining total throughput. Most A/D converters have a fixed
input range, typically ±5V. The analog front end amplifies low level signals and adjusts bipolar signals to
match the A/D converter's standard input.
A poorly designed analog front end will show up very quickly in the throughput specifications - some designs
may have a high throughput in only one or two ranges, but is slower at other ranges. The PC-CARD-
DAS16/330 achieves 330 kHz throughput in all ranges.
Triggering and transfer
A trigger is the event that begins an acquisition/transfer cycle. The trigger source used is programmable. There
are three possible trigger types:
ƒ Internal programmable pacer output
ƒ Software trigger
ƒ External hard-wired trigger
The internal programmable pacer output trigger is the quotient of two 16-bit counters dividing a 10 MHz or
1 MHz pulse derived from a 10 MHz crystal oscillator. The trigger may be used to trigger any number of paced
conversions. A single conversion may be triggered by software at any time. The external trigger, pacer clock
and interrupt signals can be used to control conversions and synchronize to external events.
After a conversion is made, the sample is loaded in a FIFO buffer from which it may be retrieved one sample at
a time or in blocks via REP-INSW transfers.
FIFO size and design
The FIFO buffer stores samples from the A/D converter as they are being converted. When a block of samples
is ready and when the PC is ready, the FIFO is emptied into system memory. A properly designed FIFO of the
correct size is required for Windows, or samples will be lost at all but the slowest speeds.
Design of the FIFO is critical. Typically, FIFO designs employ a half-full transfer initiation circuit. The transfer
request is made when the FIFO is half full. Samples continue to fill the second half of the FIFO while the CPU
responds to the transfer request and transfers data to system memory.
The PC-CARD-DAS16/330 has a 4096-sample FIFO buffer - we have determined through extensive testing
that this size is optimum.
A/D pacer clock
Many analog acquisitions can be handled by a simple on-board rate divider that is created by combining a
crystal oscillator with a programmable counter. For those applications, the on-board 82C54 programmable rate
generator (counter) supplies the pacing. Some applications may require more flexible rate control.
Analog conversions can be externally paced, and thereby synchronized with events external to the PC.
Conversions can be held off until some external event, such as a not-to-exceed (alarm) condition is met.
Conversions can be externally gated so that samples are taken only when an event of interest is occurring, such
as a process going over normal limits.
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