Measurement Computing CIO-DAS16/M1/16 - Manual (Page 22)

Input High 2.0 volts min, 5.5 volts absolute max
Input Low 0.8 volts max,
−0.5 volts absolute min
Interrupts Programmable levels 2 to 7, 10 to12, 14, 15; Positive-edge triggered
Interrupt enable Programmable
Interrupt sources A/D End-of-conversion, A/D FIFO half full, A/D Residual Counter
Counter section
Counter type 82C54
Configuration 3 down-counters, 16 bits each
Counter 0 - General purpose counter or ADC residual sample counter when using
REPINSW.
Source: Programmable: external (CTR0IN), internal (1 MHz osc) or ADC
pacer (when using REPINSW).
Gate: Programmable source: external (DIN2) or internal (when using
REPINSW)
Output: Programmable: user connector, end-of-acquisition interrupt (when
using REPINSW).
Counter 1 - ADC Pacer Lower Divider
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source: external (DIN1) or
internal.
Output: Chained to Counter 2 Clock.
Counter 2 - ADC Pacer Upper Divider
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source: external (DIN1) or
internal.
Output: ADC Pacer clock, output available at user connector (CTR2 Out).
Clock input frequency 10 Mhz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input)
50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min
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