Measurement Computing CIO-DAS16/M1/16 - Manual (Page 15)

WRITE
DO0 DO1 DO2 DO3 Not Used Not Used Not Used Not Used
0 1 3 2 4 5 6 7
All of the four bits are latched TTL outputs.
The WRITE to this register also clears external trigger latched bit.
5.5 STATUS REGISTER
BASE ADDRESS + 8 Example, 308h, 776 Decimal
READ
MA0 MA1 MA2 MA3 INTB OVRN U/B EOC
0 1 2 3 4 5 6 7
Description of Status Register read bits:
EOC - End of Conversion. 1 = Busy, 0 = Conversion complete.
U/B - Unipolar/Bipolar. 0 = Bipolar A/D input, 1 = Unipolar A/D input.
OVRN- FIFO Overrun status. 0 = has not overrun (not full), 1 = overrun (FIFO is full).
(The OVRN bit is latched. The latch is cleared by a FIFO clear write to Base + 2).
INTB - State of interrupt flop. Latched. 0 = no interrupt occurred, 1 = interrupt occurred.
MA3:0 - Current channel mux setting for next conversion.
WRITE
The write function clears the interrupt.
5.6 INTERRUPT AND PACER CONTROL REGISTER
BASE ADDRESS +9 Example, 309h, 777 Decimal
READ/WRITE
TS0 TS1 - BMDE INT1 INT2 INT4 INT8
0 1 2 3 4 5 6 7
Burst Mode is a method of performing pseudo-simultaneous sample-and-hold on a specified number of channels
without using an external sample-and-hold board or providing individual sample-and-hold amplifiers or A/D
converters on each channel. When Burst Mode is selected, each channel in the burst is sampled at the maximum
speed of the A/D converter (1 MHz) and the time between bursts is set by TS1:0. The channels contained in the burst
are set by register BASE +2 and the number of channels in the burst are set by register BASE +Ah.
The interrupts are enabled/disabled and selected using the following four bits. The routing of the interrupts is set by
the TS0/TS1 bits. When TS1 is set to 1 (not Software conversions), the interrupt is generated by FIFO Half-Full.
That is, when the A/D is sampling and reaches 512 samples, this interrupt is generated to allow the user to perform a
REP INSW block transfer. When TS0 and TS1 are set to 0, Software triggers are enabled in Low Speed Mode and the
interrupts are generated at the end of each FIFO write. That is, when a sample of data is written into the FIFO an
interrupt is generated to allow the user to read it. Finally, when performing REP INSW, if the number of samples is
not a 512 block multiple, there will be a residual number of samples to be taken. By setting the Enhanced bit (register
Base + 11), when RCG is set, the residual samples are to be taken and the interrupts are generated from the residual
counter - Counter 0 (see Base +Bh for further description).
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