Measurement Computing CIO-DAS16/M1/16 - Manual (Page 16)

INT4:1 - Interrupt selection
Table 5-2. Interrupt Coding
15 1 1 1 1
14 0 1 1 1
Not Available 1 0 1 1
12 0 0 1 1
11 1 1 0 1
10 0 1 0 1
Not Available 1 0 0 1
Not Available 0 0 0 1
7 1 1 1 0
6 0 1 1 0
5 1 0 1 0
4 0 0 1 0
3 1 1 0 0
2 0 1 0 0
Not Available 1 0 0 0
DISABLED 0 0 0 0
INTERRUPT INT1 INT2 INT4 INT8
BMDE - Burst Mode Enable. 0 = disable, 1 = enabled. The number of channels in the burst are set in BASE +Ah
register.
TS1:0 - A/D trigger source
Table 5-3. Trigger Source Coding
Internal Paced 1 1
Rising External Pacer 0 1
Software Trigger X 0
TRIGGER SOURCE TS0 TS1
To perform conversions in Software Mode, the A/D converter samples at 1 MHz. The maximum delay from the
trigger to the first 1 MHz convert pulse is < 1 uSec, since the trigger enables the 1 MHz pulse train to pass through to
the counter circuit to count 3 pulses which in turn will generate the FIFO write pulse. Therefore, the maximum delay
from the Software Trigger (Base + 0 Write) is 3 uSec.
To perform conversions in Pacer modes, the following sequence must be followed by the program:
The counter (Internal Paced) or DIN0 (External Paced) must be set.
Set the Pacer generator, TS1/0, appropriately.
To initiate the conversions, perform a WRITE to Base + 0 (as in Software Mode) or set an external trigger/gate.
To stop conversions, perform a Base + 9 Write cycle. If using an external trigger, the clearing of the trigger pulse will
end conversions.
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