Altera MAX V CPLD Development Board - Manual (Page 16)

2–10 Chapter 2: Board Components
Connectors
MAX V CPLD Development Board Reference Manual January 2011 Altera Corporation
Table 2–16 lists the GPIO headers component reference and the manufacturing
information.
PC Speaker Header
The development board includes one PC speaker header which connects to the MAX
V CPLD I/O bank 2. The speaker header also supports a compatible standard
four-pin motherboard speaker.
J7.24 GPIO connector B pin BGPIO_22
Variable VCCIO
voltage
(1.2-V to 3.3-V)
J15
J7.25 GPIO connector B pin BGPIO_23 J14
J7.26 GPIO connector B pin BGPIO_24 K16
J7.27 GPIO connector B pin BGPIO_25 K15
J7.28 GPIO connector B pin BGPIO_26 K14
J7.29 Power 3.3VIN_CONN 3.3-V —
J7.30 Ground GND — —
J7.31 GPIO connector B pin BGPIO_27
Variable VCCIO
voltage
(1.2-V to 3.3-V)
L16
J7.32 GPIO connector B pin BGPIO_28 L15
J7.33 GPIO connector B pin BGPIO_29 L14
J7.34 GPIO connector B pin BGPIO_30 M16
J7.35 GPIO connector B pin BGPIO_31 M15
J7.36 GPIO connector B pin BGPIO_32 M14
J7.37 GPIO connector B pin BGPIO_33 L13
J7.38 GPIO connector B pin BGPIO_34 M13
J7.39 GPIO connector B pin BGPIO_35 N14
J7.40 GPIO connector B pin BGPIO_36 N13
Table 2–9. GPIO Header B Schematic Signal Names and Functions
Board Reference Description
Schematic Signal
Name
I/O Standard
MAX V CPLD Device
Pin Number
Table 2–10. GPIO Headers Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturer
Part Number
Manufacturer Website
J6, J7 GPIO headers JMSCONN Technology 217040SE www.jmsconn.com