Altera Stratix II GX Embedded Gigabit Ethernet MAC/PHY - Manual (Page 14)

Stratix II GX Embedded Gigabit Ethernet MAC / PHY
User's Guide
Version 1.0 - October 2005
TB_TXFRAMES Frames
Sets the number of frames that are generated by
the frame Generator connected to the Core
transmit FIFO interface.
5
TB_RXIPG Bytes
Sets the inter-packet gap (IGP) used by the
Ethernet Frame generator when generating
frames to the RX PHY interface.
12
TB_LENSTART Bytes
Defines the payload length of the first frame
generated by the Ethernet and FIFO models.
100
TB_LENSTEP Bytes
Frame payload length increment. During
simulation frames are generated starting from
"length of first frame" incrementing with each
frame generated.
1
TB_LENMAX Bytes
Defines the payload maximum length used by the
Ethernet Generator models. This value specifies
the wrap around for the frame length of generated
frames. I.e. if the frame length increment would
exceed this value it wraps around to zero. Can be
used to test frame length error detection, when set
to any value larger than the MAC length
configuration.
1500
TB_ENA_PADDING Boolean
If enabled, RX PHY Generator model generated
frames are padded to 64 octets in length (normal
mode). If disabled, no padding occurs and
erroneous frames will be sent to the MAC RX.
True
TB_ENA_VLAN Boolean
If enabled, all frames sent/received will be VLAN
type of frames
False
TB_STOPREAD Frames
Inhibits the Testbench RX FIFO monitor reading
the RX FIFO, after this amount of frames has
been sent to the RX.
Can be used to test Flow-Control behaviour. If
more frames are received, the FIFO will get filled.
When the threshold level is reached, a Pause-
Frame will be generated by the MAC TX. If set to
0, the RX FIFO read is never paused.
0
TB_HOLDREAD
RX FIFO
clocks
Number of clock cycles, the RX FIFO should not
be read after it has been stopped. Only relevant if
the previous configuration (read stop) was set to a
non-null value.
After this number of RX FIFO clock cycles, the RX
FIFO will be emptied again.
10
TB_TX_FF_ERR Boolean
Enable Transmit Error Generation the Core
Transmit Interface. When selected, the transmit
FIFO signal ff_tx_err is asserted with
ff_tx_eop
to signal an Error. When disabled,
the FIFO error is signalled, ff_tx_err is never
set to '1'.
False
TB_PAUSECONTROL Boolean
If enabled (true) the Testbench will stop the RX
(PHY) Frame generator, if the MAC sends a
True
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