Altera ALTPLL (Phase-Locked Loop) IP Core - Manual

ALTPLL (Phase-Locked Loop) IP Core User Guide
2014.08.18
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The Altera Phase-Locked Loop (ALTPLL) IP core implements phase lock loop (PLL) circuitry. A PLL is a
feedback control system that automatically adjusts the phase of a locally generated signal to match the phase
of an input signal. PLLs operate by producing an oscillator frequency to match the frequency of an input
signal. In this locked condition, any slight change in the input signal first appears as a change in phase
between the input signal and the oscillator frequency.
This phase shift then acts as an error signal to change the frequency of the local PLL oscillator to match the
input signal. The locking-onto-a-phase relationship between the input signal and the local oscillator accounts
for the name phase-locked loop. PLLs are often used in high-speed communication applications
You can use the Quartus
®
II IP Catalog and parameter editor to specify PLL parameters .
This IP core is not supported for Arria 10 designs. Note:
Related Information
• Introduction to Altera IP Cores
• Altera IP Release Notes
ALTPLL Features
The PLL types, operation modes, and advanced features are available for configuration in the ALTPLL IP
core. Each PLL feature includes a table that compares the PLL feature in the supported devices, and describes
the relevant parameter settings.
Phase-Locked Loop
The Phase-Locked Loop (PLL) is a closed-loop frequency-control system that compares the phase difference
between the input signal and the output signal of a voltage-controlled oscillator (VCO). The negative feedback
loop of the system forces the PLL to be phase-locked.
PLLs are widely used in telecommunications, computers, and other electronic applications. You can use the
PLL to generate stable frequencies, recover signals from a noisy communication channel, or distribute clock
signals throughout your design.
ISO
9001:2008
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