Avalue EBM-CX700 - Manual (Page 63)

User’s Manual
EBM-CX700 Series User’s Manual 63
3.5.3.3 CPU & PCI Bus Control
Item Options Description
PCI Master 0 WS Write
Enabled
Disabled
To write PCI bus while zero wait state is executed.
PCI Delay Transaction
Enabled
Disabled
This feature is used to meet the latency of PCI cycles to
and from the ISA bus. The ISA bus is much, much slower
than the PCI bus. Thus, PCI cycles to and from the ISA
bus take a longer time to complete and this slows the PCI
bus down.
However, enabling PCI Delayed Transaction enables
the chipset's embedded 32-bit posted write buffer to
support delayed transaction cycles. This means that
transactions to and from the ISA bus are buffered and the
PCI bus can be freed to perform other transactions while
the ISA transaction is underway.
This option should be enabled for better performance
and to meet PCI 2.1 specifications. “Disabled” is set only
if the PCI cards cannot work properly or if an ISA card
that is not PCI 2.1 compliant is used.
DRDY_Timing
Slowest
Default
Optimize
Allows to set the timing for each cycle that data is
transferred.