ADLINK PCI-9820 - Manual (Page 39)

Operation Theory
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Fig 4.12 and Fig 4.13 show the input and output timing requirements.
T
w
SSI_TRIG1
T
w
= 2 - 3 TIMEBASE clocks
Figure 4.12 SSI_TRIG1 output signal timing
T
w
SSI_TRIG1
T
w
= 20 ns minimum
Figure 4.13 SSI_TRIG1 input signal timing
4.7.3 SSI_TRIG2 and SSI_START_OP
As an output, the SSI_TRIG2 signal is a clocked SSI_TRIG1 signal by
TIMEBASE, as illustrated in Fig 4.14.
T
w
SSI_TRIG1
T
w
= 2 TIMEBASE clocks
SSI_TRIG2
TIMEBASE
Figure 4.14 SSI_TRIG2 output signal timing
As an input, the PCI-9820 accepts the SSI_TRIG2 signal to be the source of
a one-clock delayed trigger event. The controller on the PCI-9820 will then
compensate the one-clock delay if using SSI_TRIG2 as the source of trigger
event. The signal is configured in the rising edge-detection mode.