ADLINK DAQe-2006 - Manual (Page 69)

Operation Theory 57
4.3 Digital I/O
The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card contains 24
lines of general-purpose digital I/O (GPIO) which is provided
through the 82C55A chip.
The 24-line GPIO are separated into three ports: Port A, Port B
and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of
each port can be programmed individually to be either inputs or
outputs. Upon system startup or reset, all the GPIO pins are reset
to high impedance inputs.
The DAQ/DAQe/PXI-2010 also provides two digital inputs per
channel (SDI from J5), which are sampled simultaneously with an
analog signal input and is stored with the 14-bit AD data. Refer to
Figure 4.1 for the more details.
4.4 General Purpose Timer/Counter Operation
Two independent 16-bit up/down timer/counter are designed
within FPGA for various applications. They have the following fea-
tures:
X Count up/down controlled by hardware or software
X Programmable counter clock source (internal or external
clock up to 10 MHz)
X Programmable gate selection (hardware or software con-
trol)
X Programmable input and output signal polarities (high active
or low active)
X Initial count can be loaded from software
X Current count value can be read-back by software without
affecting circuit operation
Timer/Counter functions basics
Each timer/counter has three inputs that can be controlled via
hardware or software. They are clock input (GPTC_CLK), gate
input (GPTC_GATE), and up/down control input
(GPTC_UPDOWN). The GPTC_CLK input provides a clock
source input to the timer/counter. Active edges on the GPTC_CLK
input make the counter increment or decrement. The