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Switching waveforms, Read cycle timing – Cypress CY7C1339G User Manual

Page 11

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CY7C1339G

Document #: 38-05520 Rev. *F

Page 11 of 18

Switching Waveforms

Read Cycle Timing

[18]

Note:

18. On this diagram, when CE is LOW, CE

1

is LOW, CE

2

is HIGH and CE

3

is LOW. When CE is HIGH, CE

1

is HIGH or CE

2

is LOW or CE

3

is HIGH.

tCYC

t

CL

CLK

ADSP

t

ADH

t

ADS

ADDRESS

t

CH

OE

ADSC

CE

tAH

tAS

A1

tCEH

tCES

GW, BWE,

BW[A:D]

Data Out (Q)

High-Z

tCLZ

tDOH

tCO

ADV

tOEHZ

tCO

Single READ

BURST READ

tOEV

tOELZ

tCHZ

ADV
suspends
burst.

Burst wraps around
to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1)

Q(A2)

Q(A2 + 1)

Q(A2 + 3)

A2

A3

Deselect
cycle

Burst continued with
new base address

DON’T CARE

UNDEFINED

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