Sram read cycle, Ac switching characteristics, Switching waveforms – Cypress CY14E256L User Manual
Page 9
CY14E256L
Document Number: 001-06968 Rev. *F
Page 9 of 18
AC Switching Characteristics
SRAM Read Cycle
Parameter
Description
25 ns
35 ns
45 ns
Unit
Min
Max
Min
Max
Min
Max
Cypress
Parameter
Alt
t
ACE
t
ELQV
Chip Enable Access Time
25
35
45
ns
t
RC
t
AVAV,
t
ELEH
Read Cycle Time
25
35
45
ns
t
AA
t
AVQV
Address Access Time
25
35
45
ns
t
DOE
t
GLQV
Output Enable to Data Valid
10
15
20
ns
t
OHA
t
AXQX
Output Hold After Address Change
5
5
5
ns
t
LZCE
t
ELQX
Chip Enable to Output Active
5
5
5
ns
t
HZCE
t
EHQZ
Chip Disable to Output Inactive
10
13
15
ns
t
LZOE
t
GLQX
Output Enable to Output Active
0
0
0
ns
t
HZOE
t
GHQZ
Output Disable to Output Inactive
10
13
15
ns
t
PU
t
ELICCH
Chip Enable to Power Active
0
0
0
ns
t
PD
t
EHICCL
Chip Disable to Power Standby
25
35
45
ns
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled
Figure 8. SRAM Read Cycle 2: CE and OE Controlled
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Notes
9. WE and HSB must be HIGH during SRAM Read cycles.
10. Device is continuously selected with CE and OE both Low.
11. Measured ±200 mV from steady state output voltage.