Cypress CY14B101Q3 - Manual (Page 22)

Document #: 001-50091 Rev. *A Revised February 2, 2009 Page 22 of 22
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PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3
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Document Title: CY14B101Q1/CY14B101Q2/CY14B101Q3 1 MBit (128K x 8) Serial SPI nvSRAM
Document Number: 001-50091
REV. ECN NO.
Orig. of
Change
Submission
Date
Description of Change
** 2607408 GSIN/
GVCH/AESA
12/19/08 Updated the “Feature” section
Updated nvSRAM STORE, RECALL, AutoStore Enable/Disable sections
Removed Soft Sequence
Added SPI instructions for STORE, RECALL, AutoStore Enable and Disable
Updated SPI with following changes:
-- Added more information for protocol
-- Added four new SPI instruction
-- WEN bit cleared on CS going high edge after Write instructions and four
nvSRAM special instructions
Added RDY bit to Status Register for indicating Store/Recall in progress
Other changes as per new EROS
Removed 8 SOIC package
Added two new 8DFN packages
Changed tCO parameter to 9 ns
*A 2654487 GVCH/PYRS 02/04/2009 Moved from Advance information to Preliminary
Changed part number from CY14B101QxA to CY14B101Qx
Updated pin description of V
CAP
pin
Updated Device operation and SPI peripheral interface description
Added Factory setting values for BP1, BP2 and WPEN bits
Updated Real Time Clock operation description
Changed I
CC2
from 5mA to 10mA
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