Hardware store cycle, Switching waveforms, Write latch set write latch not set – Cypress CY14B104M User Manual
Page 22
PRELIMINARY
CY14B104K, CY14B104M
Document #: 001-07103 Rev. *K
Page 22 of 31
Hardware STORE Cycle
Parameters
Description
20 ns
25 ns
45 ns
Unit
Min
Max
Min
Max
Min
Max
t
DHSB
HSB To Output Active Time when write latch not set
20
25
25
ns
t
PHSB
Hardware STORE Pulse Width
15
15
15
ns
Switching Waveforms
Figure 15. Hardware STORE Cycle
Figure 16. Soft Sequence Processing
t
PHSB
t
PHSB
t
DELAY
t
DHSB
t
DELAY
t
STORE
t
HHHD
t
LZHSB
Write latch set
Write latch not set
HSB (IN)
HSB (OUT)
DQ (Data Out)
RWI
HSB (IN)
HSB (OUT)
RWI
HSB pin is driven high to V
CC
only by Internal
SRAM is disabled as long as HSB (IN) is driven low.
HSB driver is disabled
t
DHSB
100kOhm resistor,
Address #1
Address #6
Address #1
Address #6
Soft Sequence
Command
t
SS
t
SS
CE
Address
V
CC
t
SA
t
CW
Soft Sequence
Command
t
CW
Notes
32. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
33. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.