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Cypress CY7C1324H User Manual

Page 5

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CY7C1324H

Document #: 001-00208 Rev. *B

Page 5 of 15

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

I

DDZZ

Sleep mode standby current

ZZ > V

DD

– 0.2V

40

mA

t

ZZS

Device operation to ZZ

ZZ > V

DD

– 0.2V

2t

CYC

ns

t

ZZREC

ZZ recovery time

ZZ < 0.2V

2t

CYC

ns

t

ZZI

ZZ Active to sleep current

This parameter is sampled

2t

CYC

ns

t

RZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

ns

Truth Table

[2, 3, 4, 5]

Cycle Description

ADDRESS

Used

CE

1

CE

2

CE

3

ZZ

ADSP

ADSC

ADV

WE

OE

CLK

DQ

Deselected Cycle,
Power-down

None

H

X

X

L

X

L

X

X

X

L-H

Tri-State

Deselected Cycle,
Power-down

None

L

L

X

L

L

X

X

X

X

L-H

Tri-State

Deselected Cycle,
Power-down

None

L

X

H

L

L

X

X

X

X

L-H

Tri-State

Deselected Cycle,
Power-down

None

L

L

X

L

H

L

X

X

X

L-H

Tri-State

Deselected Cycle,
Power-down

None

X

X

X

L

H

L

X

X

X

L-H

Tri-State

Sleep Mode, Power-down

None

X

X

X

H

X

X

X

X

X

X

Tri-State

Read Cycle, Begin Burst

External

L

H

L

L

L

X

X

X

L

L-H

Q

Read Cycle, Begin Burst

External

L

H

L

L

L

X

X

X

H

L-H

Tri-State

Write Cycle, Begin Burst

External

L

H

L

L

H

L

X

L

X

L-H

D

Read Cycle, Begin Burst

External

L

H

L

L

H

L

X

H

L

L-H

Q

Read Cycle, Begin Burst

External

L

H

L

L

H

L

X

H

H

L-H

Tri-State

Read Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

L

L-H

Q

Read Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

H

L-H

Tri-State

Read Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

L

L-H

Q

Read Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

H

L-H

Tri-State

Write Cycle, Continue Burst

Next

X

X

X

L

H

H

L

L

X

L-H

D

Write Cycle, Continue Burst

Next

H

X

X

L

X

H

L

L

X

L-H

D

Read Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

L

L-H

Q

Read Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

H

L-H

Tri-State

Read Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

L

L-H

Q

Read Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

H

L-H

Tri-State

Write Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

L

X

L-H

D

Write Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

L

X

L-H

D

Notes:

2. X = “Don't Care.” H = Logic HIGH, L =Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW

A

, BW

B

) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals (BW

A

, BW

B

),

BWE, GW = H.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

4. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW

[A: B]

. Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle

5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Tri-State when OE

is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW)

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