Cypress CY7C1324H - Manual (Page 10)

CY7C1324H
Document #: 001-00208 Rev. *B Page 10 of 15
Timing Diagrams
Read Cycle Timing [15]
Note:
15. On this diagram, when CE is LOW, CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH, CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
tCYC
t
CL
CLK
tADH tADS
ADDRESS
t
CH
tAH tAS
A1
tCEH tCES
Data Out (Q) High-Z
tCLZ
tDOH
tCDV
tOEHZ
tCDV
Single READ BURST
READ
tOEV tOELZ
tCHZ
Burst wraps around
to its initial state
t
ADVH
t
ADVS
t
WEH
t
WES
tADH tADS
Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3)
A2
ADV suspends burst.
Deselect Cycle
DON’T CARE UNDEFINED
ADSP
ADSC
GW, BWE,BW
[A:B]
CE
ADV
OE
[+] Feedback