Cypress CY7C1324H - Manual (Page 12)

CY7C1324H
Document #: 001-00208 Rev. *B Page 12 of 15
Read/Write Timing [15, 17, 18]
Notes:
17. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
18. GW is HIGH.
Timing Diagrams (continued)
tCYC
t
CL
CLK
tADH tADS
ADDRESS
t
CH
tAH tAS
A2
tCEH tCES
Single WRITE
D(A3)
A3 A4
BURST READ Back-to-Back READs
High-Z
Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)
t
WEH
t
WES
t
OEHZ
tDH tDS
tCDV
tOELZ
A1 A5 A6
D(A5) D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE UNDEFINED
ADSP
ADSC
BWE, BW [A:B]
CE
ADV
OE
Data In (D)
Data Out (Q)
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