Maxim Integrated 73M1866B/73M1966B Implementers Guide - Manual (Page 6)

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016
6 Rev. 1.3
3 Device Configuration and Initialization
3.1 Host-Side Device (73M1906B) Configuration
The Host-side device configuration and initialization includes the following steps:
1. Reset and Disable Interrupts
2. PCLK Clock Recovery and PLL
3. Call Progress Monitor Reset
4. PCM Interface Configuration
3.1.1 Reset and Disable Interrupts
The recommended way to deal with the first interrupt after reset is to disable the interrupt generation until
the system is ready to handle them.
Despite being in Register 0x05, ENAPOL is not an interrupt masking register and should not be
disabled.
The registers used in this procedure are:
0x03 GPIO7 GPIO6 GPIO5 PCLKDT RGMON DET SYNL RGDT
Read X X X X X X X X
0x05 ENGPIO7 ENGPIO6 ENGPIO5 ENPCLKDT ENAPOL ENDET ENSYNL ENRGDT
Write 0 0 0 0 1 0 0 0
Begin
1. Release RST.
2. Wait for Interrupt.
3. Set ENGPIO[7:5] = ENPCLKD = ENDET = ENSYNL = ENRGDT = 0,
set ENAPOL = 1 (RG05 = 0x08).
4. Read RG03 to clear the register value and de-assert the INT pin.
End
Start
Release RST
INT?
No
Yes
Write RG05=0x08
Read
RG03=X
End