Maxim Integrated 73M1866B/73M1966B Implementers Guide - Manual (Page 3)

UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide
Rev. 1.3 3
Table of Contents
1 Introduction ......................................................................................................................................... 4
1.1 Procedure Conventions ................................................................................................................ 4
1.2 Read-Modify-Write Procedure ...................................................................................................... 4
2 Hardware Requirements ..................................................................................................................... 5
2.1 Reset ............................................................................................................................................. 5
2.2 SPI Interface ................................................................................................................................. 5
2.3 PCM Interface ............................................................................................................................... 5
2.4 Interrupts ....................................................................................................................................... 5
3 Device Configuration and Initialization ............................................................................................ 6
3.1 Host-Side Device (73M1906B) Configuration ............................................................................... 6
3.1.1 Reset and Disable Interrupts ........................................................................................... 6
3.1.2 PCLK Clock Recovery and PLL Lock Detection .............................................................. 7
3.1.3 Call Progress Monitor Reset ............................................................................................ 8
3.1.4 PCM Interface Configuration ........................................................................................... 9
3.2 Line-Side Device (73M1916) Configuration ................................................................................ 10
3.2.1 Barrier Synchronization Recovery ................................................................................. 10
3.2.2 Receiver DC Offset Calibration ...................................................................................... 13
3.2.3 Initial Line State Configuration ....................................................................................... 15
4 On-Hook Procedures ........................................................................................................................ 17
4.1 CID Mode .................................................................................................................................... 17
4.2 Off-Hook Request ....................................................................................................................... 18
4.3 Ring Detection and Line Voltage Reversal ................................................................................. 20
4.4 Line-in-use and Loss of Battery Feed ......................................................................................... 22
5 Off-Hook Procedures ........................................................................................................................ 23
5.1 Barrier Synch Loss...................................................................................................................... 23
5.2 On-hook Request ........................................................................................................................ 23
5.3 Parallel Pickup Event Detection .................................................................................................. 23
6 Interrupt Processing ......................................................................................................................... 24
6.1 GPIO Interrupt ............................................................................................................................. 24
6.2 PCLKDT Interrupt ....................................................................................................................... 25
6.3 DET Interrupt .............................................................................................................................. 25
6.4 SYNL Interrupt ............................................................................................................................ 26
6.5 RGDT and RGMON Interrupts .................................................................................................... 26
7 Register Summary ............................................................................................................................ 27
8 Related Documentation .................................................................................................................... 28
9 Contact Information .......................................................................................................................... 28
Revision History ........................................................................................................................................ 29
Figures
Figure 1: SPI Write Transaction
.................................................................................................................... 5
Figure 2: SPI Read Transaction .................................................................................................................... 5
Figure 3: Ring Detection ............................................................................................................................. 20
Figure 4: Battery Feed and Line-in-Use Detection ..................................................................................... 22