Cypress CY14B108M - Manual (Page 20)

PRELIMINARY
CY14B108K, CY14B108M
Document #: 001-47378 Rev. ** Page 20 of 29
Switching Waveforms
Figure 10. SRAM Write Cycle 2: CE Controlled [3, 18, 19, 20]
Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled
[5, 18, 19, 20, 21]
Data Output
Data Input Input Data Valid
High Impedance
Address Valid Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SA
t
SCE
t
HA
t
BW
t
PWE
Data Output
Data Input Input Data Valid
High Impedance
Address Valid Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SCE
t
SA
t
BW
t
HA
t
AW
t
PWE
(Not applicable for RTC register writes)
Note
21. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.
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