Cypress CY62158E - Manual

CY62158E MoBL
®
8-Mbit (1M x 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600
Document #: 38-05684 Rev. *D Revised June 16, 2008
Features
■ Very high speed: 45 ns
❐ Wide voltage range: 4.5V – 5.5V
■ Ultra low active power
❐ Typical active current:1.8 mA @ f = 1 MHz
❐ Typical active current: 18 mA @ f = f
max
■ Ultra low standby power
❐ Typical standby current: 2
μA
❐ Maximum standby current: 8
μA
■ Easy memory expansion with CE
1
, CE
2
and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Offered in Pb-free 44-Pin TSOP II package
Functional Description
The CY62158E MoBL
®
is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption significantly when deselected (CE
1
HIGH or
CE
2
LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. Data on the eight IO
pins (IO
0
through IO
7
) is then written into the location specified
on the address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and OE LOW while forcing the WE HIGH. Under these
conditions, the contents of the memory location specified by the
address pins appear on the IO pins.
The eight input and output pins (IO
0
through IO
7
) are placed in
a high impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE
1
LOW and CE
2
HIGH and WE
LOW). See the Truth Table on page 8 for a complete description
of read and write modes.
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines .
A0 IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN WE
OE
A
13
A
14
A
15
A
16
ROW DECODER
COLUMN DECODER
1024K x 8
ARRAY
DATA IN DRIVERS
A10
A11
A
17
CE1
CE2
A12
A
18
A
19
Logic Block Diagram
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