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Cypress CY7C1381DV25 User Manual

Page 9

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CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Document #: 38-05547 Rev. *E

Page 9 of 28

Truth Table

[4, 5, 6, 7, 8]

Cycle Description

Address

Used

CE

1

CE

2

CE

3

ZZ

ADSP

ADSC

ADV WRITE

OE

CLK

DQ

Deselected Cycle, Power

Down

None

H

X

X

L

X

L

X

X

X

L-H Tri-State

Deselected Cycle, Power

Down

None

L

L

X

L

L

X

X

X

X

L-H Tri-State

Deselected Cycle, Power

Down

None

L

X

H

L

L

X

X

X

X

L-H Tri-State

Deselected Cycle, Power

Down

None

L

L

X

L

H

L

X

X

X

L-H Tri-State

Deselected Cycle, Power

Down

None

X

X

X

L

H

L

X

X

X

L-H Tri-State

Sleep Mode, Power Down

None

X

X

X

H

X

X

X

X

X

X

Tri-State

Read Cycle, Begin Burst

External

L

H

L

L

L

X

X

X

L

L-H Q

Read Cycle, Begin Burst

External

L

H

L

L

L

X

X

X

H

L-H Tri-State

Write Cycle, Begin Burst

External

L

H

L

L

H

L

X

L

X

L-H D

Read Cycle, Begin Burst

External

L

H

L

L

H

L

X

H

L

L-H Q

Read Cycle, Begin Burst

External

L

H

L

L

H

L

X

H

H

L-H Tri-State

Read Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

L

L-H Q

Read Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

H

L-H Tri-State

Read Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

L

L-H Q

Read Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

H

L-H Tri-State

Write Cycle, Continue Burst

Next

X

X

X

L

H

H

L

L

X

L-H D

Write Cycle, Continue Burst

Next

H

X

X

L

X

H

L

L

X

L-H D

Read Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

L

L-H Q

Read Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

H

L-H Tri-State

Read Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

L

L-H Q

Read Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

H

L-H Tri-State

Write Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

L

X

L-H D

Write Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

L

X

L-H D

Notes

4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW

X

. Writes may occur only on subsequent clocks after

the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
care for the remainder of the write cycle.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

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