Cypress CY7C1381DV25 - Manual (Page 20)

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document #: 38-05547 Rev. *E Page 20 of 28
Timing Diagrams
Read Cycle Timing [25]
tCYC
t
CL
CLK
tADH tADS
ADDRESS
t
CH
tAH tAS
A1
t CEH tCES
Data Out (Q) High-Z
tCLZ
tDOH
tCDV
tOEHZ
tCDV
Single READ BURST
READ
tOEV tOELZ
tCHZ
Burst wraps around
to its initial state
t
ADVH
t
ADVS
t
WEH
t
WES
tADH tADS
Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3)
A2
ADV suspends burst
Deselect Cycle
DON’T CARE UNDEFINED
ADSP
ADSC
GW, BWE,BW
X
CE
ADV
OE
Note
25. On this diagram, when CE is LOW: CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH: CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
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