Cypress CY7C1319CV18 - Manual (Page 2)

CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
Document Number: 001-07161 Rev. *D Page 2 of 31
Logic Block Diagram (CY7C1317CV18)
Logic Block Diagram (CY7C1917CV18)
Write
Reg
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add
. Decode
Read Data Reg.
R/W
DQ
[7:0]
Output
Logic
Reg.
Reg.
Reg.
16
8
32
8
NWS
[1:0]
V
REF
W
rite Add. Decode
16
19
C
C
8
LD
Control
CQ
CQ
R/W
DOFF
5
12K x 8 A
rray
5
12K x 8 A
rray
8
Write
Reg
Write
Reg
Write
Reg
5
12K x 8 A
rray
5
12K x 8 A
rray
8
8
Write
Reg
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read
A
d
d. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
18
36
9
BWS
[0]
V
REF
W
rite Add. Decode
18
19
C
C
9
LD
Control
R/W
DOFF
512K x 9 A
rray
512K x 9 A
rray
9
Write
Reg
Write
Reg
Write
Reg
512K x 9 A
rray
512K x 9 A
rray
9
9
DQ
[8:0]
9
CQ
CQ
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