Digilent D2XL - Manual (Page 2)

Digilent D2XL Reference Manual Digilent, Inc.
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The D2XL board has been
designed to serve as a host for
various peripheral boards. The
expansion connectors on the
board mate with standard 40-pin,
100 mil spaced DIP headers
available from any catalog
distributor. Expansion connectors
provide the unregulated supply
voltage (VU), 3.3V, GND, and 37
FPGA signals to peripheral
boards, so system designers can
quickly develop application-
specific peripheral boards.
Digilent also produces a
collection of expansion boards
with commonly used devices.
See the Digilent website
(www.digilentinc.com) for a listing
of currently available boards.
Table 1 shows all signals routed
on the D2XL board. These
signals and their circuits are
described in the following
sections.
Parallel port and FPGA
configuration circuit
The D2XL board uses a DB-25
parallel port connector to route JTAG programming signals from a host computer to the FPGA. This
same connector also routes the computer’s parallel port pins to the FPGA following the EPP port
definition contained in the IEEE 1284 standard. A three-state buffer, controlled by a switch,
determines whether the JTAG port or EPP port is enabled. With this circuit, the FPGA can be
configured using the JTAG protocol over the parallel cable. The same cable can then be used (after
the switch is repositioned) to move data between the board and the host computer using the high-
speed EPP protocol. A separate JTAG header is also provided so that a dedicated programming
cable (like the Xilinx Parallel III cable) can be used.
The JTAG programming circuit follows the JTAG schematic available from Xilinx, so that the D2XL
board is fully compatible with all Xilinx programming tools. The EPP parallel port circuit follows the
guidelines in the IEEE 1284 specification, and data rates approaching 2Mbytes/second can be
achieved. JTAG and EPP connections are shown in the diagrams below.
Power Supplies
VU Unregulated power supply voltage – depends on
power supply used. Must be between 5VDC and
10VDC. Routed to regulators and expansion
connectors only.
VDD33 VCCO/VCC for all devices, routed on PCB plane.
1.5A can be drawn with less than 20mV ripple
(typical)
VDD25 FPGA VCCINT routed on PCB plane
GND System ground routed to all devices on PCB
ground plane
Programming and parallel port
PWE EPP mode write enable signal (in to FPGA)
PD0-
PD7
Bi-directional data signals
PINT Interrupt signal (out from FPGA)
PWT EPP mode wait signal (out from FPGA)
PDS EPP mode data strobe (in to FPGA)
PRS Reset signal (in to FPGA)
PAS EPP mode address strobe (in to FPGA)
On board devices
BTN1 User-controllable pushbutton input
LED1 User-controllable status LED
CLK1 CMOS oscillator connected to GCLK0
Expansion Connectors
E4-E40 E bus signals connecting the E connector to the
FPGA
F4-F14 F bus signals connecting the F connectors to the
FPGA
Table 1. D2XL board signal definitions