Digilent Cerebot Plus Board - Manual (Page 5)

Digilent Cerebot Plus Reference Manual Digilent, Inc.
www.digilentinc.com page 5 of 13
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Programming Options
The Cerebot Plus provides two in-system
programming connections, J1 and J2.
Connector J1 is the Digilent ISP connector.
This provides for in-system programming using
a Digilent JTAG3 parallel port cable or a
Digilent USB-JTAG/SPI cable. When
connecting the Digilent JTAG/SPI cables,
ensure that the VCC and GND pin labels from
the cable match to the VCC and GND pins on
the Cerebot Plus. When using a Digilent
programming cable, use the Digilent AVR
Programmer application available for download
from the Digilent web site
(
www.digilentinc.com ) to program the board.
Connector J2 is a 6-pin (3x2) header for in-
system programming using the Atmel AVRISP
(Atmel P/N ATAVRISP) programmer. When
connecting to the Cerebot Plus, the red
indicator line on the AVRISP connection plug
must be aligned with the top pins MISO and
VCC on J2.
Programming can be accomplished using
several AVR programming applications
including the Digilent AVR Programmer
(AVRP), AVRDUDE from the WinAVR tool set,
and Atmel’s AVR Studio. Programming via
AVR Studio requires use of the Atmel AVRISP
programmer hardware. See the user’s
documentation for each of these applications
for more information on board programming.
Debugging with the Atmel JTAG
ICE mk-II
Connector J6 on the Cerebot Plus is provided
for the Atmel JTAG ICE mk-II (ATJTAGICE2)
in-circuit emulator for debugging purposes.
The JTAG ICE works with the debugger in
Atmel’s AVR Studio product.
The JTAG port on the ATmega2560 must be
enabled when using the JTAG ICE. The
Cerebot Plus is shipped with the JTAG port
disabled. This port can be enabled or disabled
using a fuse bit which can be set with any of
the supported in-system programmers
described above.
Two Wire Serial Interface
The Atmel Two Wire Serial Interface (TWI)
provides a medium speed (400K bps)
synchronous serial communications bus. The
TWI interface provides master and slave
operation with up to 127 devices on the bus.
Each device is given a unique address, and
the protocol provides the ability to address
packets to a specific device or to broadcast
packets to all devices on the bus. See the
ATmega2560 data sheet for detailed
information on configuring and using the two
wire interface.
The Cerebot Plus provides two ways to
connect to a TWI bus. The TWI signals (SCL
and SDA) are available on Pmod connector JD
or on the TWI daisy chain connector J3.
Connector J3 provides two positions for
connecting to the TWI signals. By using two-
wire cables (available separately from Digilent)
a daisy chain of multiple Cerebot Plus boards
or other TWI-capable boards can be created.
The TWI bus is an open-collector bus. Devices
on the bus actively drive the signals low. The
high state on the TWI lines is achieved by pull-
up resistors when no device is driving the lines
low. One device on the TWI bus must provide
the pull-up resistors. The Cerebot Plus board
provides pull-up resistors that can be enabled
or disabled via jumper blocks on the “pullup”
positions on J3. The pull-ups are enabled by
installing shorting blocks on the “pullup”
positions and are disabled by removing the
shorting blocks. Only one device on the bus
should have the pull-ups enabled.