Cypress CY7C1361C - Manual (Page 14)

CY7C1361C
CY7C1363C
Document #: 38-05541 Rev. *F Page 14 of 31
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics Over the Operating Range
[9, 10]
Parameter Parameter Min. Max. Unit
Clock
t
TCYC
TCK Clock Cycle Time 50 ns
t
TF
TCK Clock Frequency 20 MHz
t
TH
TCK Clock HIGH Time 20 ns
t
TL
TCK Clock LOW Time 20 ns
Output Times
t
TDOV
TCK Clock LOW to TDO Valid 10 ns
t
TDOX
TCK Clock LOW to TDO Invalid 0 ns
Set-up Times
t
TMSS
TMS Set-Up to TCK Clock Rise 5 ns
t
TDIS
TDI Set-Up to TCK Clock Rise 5 ns
t
CS
Capture Set-Up to TCK Rise 5 ns
Hold Times
t
TMSH
TMS Hold after TCK Clock Rise 5 ns
t
TDIH
TDI Hold after Clock Rise 5 ns
t
CH
Capture Hold after Clock Rise 5 ns
Notes:
9. t
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
t
TL
Test Clock
(TCK)
1 2 3 4 5 6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH tTMSS
tTDIH tTDIS
tTDOX
tTDOV
DON’T CARE UNDEFINED
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