Cypress CY7C1365C - Manual (Page 5)

CY7C1365C
Document #: 38-05690 Rev. *E Page 5 of 18
Pin Descriptions
Name TQFP I/O Description
A0, A1, A 37,36,32,33,34,35,44,45,46,
47,48,49,50,81,82,99,100
92 (for 2 Chip Enable Version)
43 (for 3 Chip Enable Version) Input-
Synchronous
Address Inputs used to select one of the 256K address
locations. Sampled at the rising edge of the CLK if ADSP or ADSC
is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed
the 2-bit counter.
BW
A,
BW
B,
BW
C,
BW
D
93,94,
95,96 Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to
conduct Byte Writes to the SRAM. Sampled on the rising edge of
CLK.
GW 88 Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on
the rising edge of CLK, a global write is conducted (ALL bytes are
written, regardless of the values on BW
[A:D]
and BWE).
BWE 87 Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge
of CLK. This signal must be asserted LOW to conduct a Byte Write.
CLK 89 Input-Clock Clock Input. Used to capture all synchronous inputs to the device.
Also used to increment the burst counter when ADV is asserted LOW,
during a burst operation.
CE
1
98 Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of
CLK. Used in conjunction with CE
2
and CE
3
to select/deselect the
device. ADSP is ignored if CE
1
is HIGH. CE 1
is sampled only when
a new external address is loaded.
CE
2
97 Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of
CLK. Used in conjunction with CE
1
and CE
3
to select/deselect the
device. CE
2
is sampled only when a new external address is loaded.
CE
3
92 (for 3 Chip Enable Version) Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of
CLK. Used in conjunction with CE
1
and CE
2
to select/deselect the
device. CE
3
is assumed active throughout this document for BGA.
CE
3
is sampled only when a new external address is loaded.
OE 86 Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the
direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a Read cycle when
emerging from a deselected state.
ADV 83 Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When
asserted, it automatically increments the address in a burst cycle.
ADSP 84 Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of
CLK, active LOW. When asserted LOW, addresses presented to the
device are captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized. ASDP is ignored when CE
1
is deasserted
HIGH.
ADSC 85 Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of
CLK, active LOW. When asserted LOW, addresses presented to the
device are captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized.
ZZ 64 Input-
Asynchronous
ZZ “sleep” Input, active HIGH. When asserted HIGH places the
device in a non-time-critical “sleep” condition with data integrity
preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
DQs 52,53,56, 57,58,59, 62,63,68,
69,72,73,74,75,78,79,2,3,6,7,
8,9,12,13,18,19,22,23,24,25,
28,29 I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip
data register that is triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory location specified by
the addresses presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQs are
placed in a tri-state condition.
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