beautypg.com

Figure 7, Or the, Figure 8 – Cypress CY7C028V User Manual

Page 10: Switching waveforms

background image

CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Document #: 38-06078 Rev. *B

Page 10 of 18

Notes

20. R/W must be HIGH during all address transitions.
21. A write occurs during the overlap (t

SCE

or t

PWE

) of a LOW CE or SEM and a LOW UB or LB.

22. t

HA

is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t

PWE

or (t

HZWE

+ t

SD

) to allow the I/O drivers to turn off and data to be placed on

the bus for the required t

SD

. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t

PWE

.

24. To access RAM, CE = V

IL

, SEM = V

IH

.

25. To access upper byte, CE = V

IL

, UB = V

IL

, SEM = V

IH

.

To access lower byte, CE = V

IL

, LB = V

IL

, SEM = V

IH

.

26. Transition is measured

±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.

27. During this period, the I/O pins are in the output state, and input signals must not be applied.
28. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.

Switching Waveforms

(continued)

t

AW

t

WC

t

PWE

t

HD

t

SD

t

HA

CE

R/W

OE

DATA OUT

DATA IN

ADDRESS

t

HZOE

t

SA

t

HZWE

t

LZWE

Figure 7. Write Cycle No. 1: R/W Controlled Timing

[20, 21, 22, 23]

[26]

[26]

[23]

[24,25]

NOTE 27

NOTE 27

t

AW

t

WC

t

SCE

t

HD

t

SD

t

HA

CE

R/W

DATA IN

ADDRESS

t

SA

Figure 8. Write Cycle No. 2: CE Controlled Timing

[20, 21, 22, 28]

[24,25]

[+] Feedback

This manual is related to the following products: