Cypress HOTLink II CYV15G0104TRB - Manual (Page 3)

CYV15G0104TRB
Document #: 38-02100 Rev. *B Page 3 of 27
INA1+
INA1–
INA2+
INA2–
INSELA
Clock &
Data
Recovery
PLL
Shif
ter
LFIA
10 RXDA[9:0]
Receive
Signal
Monitor
Ou
tp
ut
Regi
ste
r
RXCLKA+
RXCLKA– ÷2
JTAG
Boundary
Scan
Controller
TDO
TMS
TCLK
TDI
RESET
Reclocking Deserializer Path Block Diagram
TRST
RXPLLPDA
SPDSELA
ULCA
RXRATEA
10
BIST LFSR
10
RXBISTA[1:0]
LDTDEN
SDASEL[2..1]A[1:0]
ROUTA1+
ROUTA1–
ROUTA2+
ROUTA2–
ROE[2..1]A
Bit-Rate Clock
Character-Rate Clock
Reclocker
RECLKOA
R
e
gi
st
er
Recovered Character Clock Recovered Serial Data
TRGCLKA
x2
TRGRATEA
REPDOA
BISTSTA
Clock Multiplier
Output PLL
ROE[2..1]A
Shif
ter
Serializer Path Block Diagram
TXRATEB
Inpu
t
R
e
gi
st
er
Ph
ase-Al
ign
Buf
fe
r
SPDSELB
REFCLKB+
REFCLKB–
Transmit PLL
Clock Multiplier
TXCLKB
Bit-Rate Clock
Character-Rate Clock
TOUTB1+
TOUTB1–
TOUTB2+
TOUTB2–
Ph
ase-Alig
n
Buf
fer
Transmit PLL
Clock Multiplier
TOE[2..1]B
TXCKSELB
= Internal Signal
TXERRB
TXCLKOB
TXDB[9:0]
10 10
PABRSTB
TOE[2..1]B
1 0
BIST LFS
R
10
TXBISTB
10
WREN
ADDR[2:0]
DATA[6:0]
Device Configuration and Control Block Diagram
= Internal Signal
RXRATEA
RXPLLPDA
TXRATEB
TXCKSELB
TOE[2..1]B
PABRSTB
Device Configuration
and Control Interface
SDASEL[2..1]A[1:0]
RXBISTA[1:0]
TXBISTB
ROE[2..1]A
TRGRATEA
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