Cypress HOTLink II CYV15G0104TRB User Manual
Page 19
CYV15G0104TRB
Document #: 38-02100 Rev. *B
Page 19 of 27
t
TXCLKR
[16, 17, 18, 19]
TXCLKB Rise Time
0.2
1.7
ns
t
TXCLKF
[16, 17, 18, 19]
TXCLKB Fall Time
0.2
1.7
ns
t
TXDS
Transmit Data Set-up Time to
TXCLKB↑ (TXCKSELB = 0)
2.2
ns
t
TXDH
Transmit Data Hold Time from TXCLKB
↑ (TXCKSELB = 0)
1.0
ns
f
TOS
TXCLKOB Clock Frequency = 1x or 2x REFCLKB Frequency
19.5
150
MHz
t
TXCLKO
TXCLKOB Period=1/f
TOS
6.66
51.28
ns
t
TXCLKOD
TXCLKOB Duty Cycle centered at 60% HIGH time
–1.9
0
ns
CYV15G0104TRB Receiver LVTTL Switching Characteristics Over the Operating Range
f
RS
RXCLKA± Clock Output Frequency
9.75
150
MHz
t
RXCLKP
RXCLKA± Period = 1/f
RS
6.66
102.56
ns
t
RXCLKD
RXCLKA± Duty Cycle Centered at 50% (Full Rate and Half Rate)
–1.0
+1.0
ns
t
RXCLKR
[16]
RXCLKA± Rise Time
0.3
1.2
ns
t
RXCLKF
[16]
RXCLKA± Fall Time
0.3
1.2
ns
t
RXDv–
[20]
Status and Data Valid Time to RXCLKA± (RXRATEA = 0) (Full Rate)
5UI–2.0
[21]
ns
Status and Data Valid Time to RXCLKA± (RXRATEA = 1) (Half Rate)
5UI–1.3
[21]
ns
t
RXDv+
[20]
Status and Data Valid Time to RXCLKA± (RXRATEA = 0)
5UI–1.8
[21]
ns
Status and Data Valid Time to RXCLKA± (RXRATEA = 1)
5UI–2.6
[21]
ns
f
ROS
RECLKOA Clock Frequency
19.5
150
MHz
t
RECLKO
RECLKOA Period=1/f
ROS
6.66
51.28
ns
t
RECLKOD
RECLKOA Duty Cycle centered at 60% HIGH time
-1.9
0
ns
CYV15G0104TRB REFCLKB Switching Characteristics Over the Operating Range
f
REF
REFCLKB Clock Frequency
19.5
150
MHz
t
REFCLK
REFCLKB Period = 1/f
REF
6.6
51.28
ns
t
REFH
REFCLKB HIGH Time (TXRATEB = 1)(Half Rate)
5.9
ns
REFCLKB HIGH Time (TXRATEB = 0)(Full Rate)
2.9
[16]
ns
t
REFL
REFCLKB LOW Time (TXRATEB = 1)(Half Rate)
5.9
ns
REFCLKB LOW Time (TXRATEB = 0)(Full Rate)
2.9
[16]
ns
t
REFD
[22]
REFCLKB Duty Cycle
30
70
%
t
REFR
[16, 17, 18, 19]
REFCLKB Rise Time (20%–80%)
2
ns
t
REFF
[16, 17, 18, 19]
REFCLKB Fall Time (20%–80%)
2
ns
t
TREFDS
Transmit Data Set-up Time to
REFCLKB - Full Rate
(TXRATEB = 0, TXCKSELB
= 1)
2.4
ns
Transmit Data Set-up Time to
REFCLKB - Half Rate
(TXRATEB = 1, TXCKSELB
= 1)
2.3
ns
t
TREFDH
Transmit Data Hold Time from REFCLKB - Full Rate
(TXRATEB= 0, TXCKSELB
= 1)
1.0
ns
Transmit Data Hold Time from REFCLKB - Half Rate
(TXRATEB = 1, TXCKSELB
= 1)
1.6
ns
CYV15G0104TRB TRGCLKA Switching Characteristics Over the Operating Range
f
TRG
TRGCLKA Clock Frequency
19.5
150
MHz
t
REFCLK
TRGCLKA Period = 1/f
TRG
6.6
51.28
ns
Notes:
17. The ratio of rise time to falling time must not vary by greater than 2:1.
18. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
19. All transmit AC timing parameters measured with 1ns typical rise time and fall time.
20. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
21. Receiver UI (Unit Interval) is calculated as 1/(f
TRG
* 20) (when TRGRATEA = 1) or 1/(f
TRG
* 10) (when TRGRATEA = 0). In an operating link this is equivalent to t
B
.
22. The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLKB± duty
cycle cannot be as large as 30%–70%.
CYV15G0104TRB AC Electrical Characteristics
(continued)
Parameter
Description
Min.
Max
Unit