Cypress 256K (32K x 8) CY62256 - Manual (Page 5)

CY62256
Document #: 38-05248 Rev. *B Page 5 of 11
Notes:
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = V
IH
.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
50% 50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
Read Cycle No. 2 [12, 13]
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATA
IN
VALID NOTE
Write Cycle No. 1 (WE Controlled)
[9, 14, 15]
16
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
WE
DATA I/O
ADDRESS
CE
DATA
IN
VALID
Write Cycle No. 2 (CE Controlled)
[9, 14, 15]