Cypress STK12C68-5 - Manual (Page 5)

STK12C68-5 (SMD5962-94599)
Document Number: 001-51026 Rev. ** Page 5 of 18
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
RECALL
cycle time, the SRAM is again
ready for Read and Write operations. The RECALL operation
does not alter the data in the nonvolatile elements. The nonvol-
atile data can be recalled an unlimited number of times.
Data Protection
The STK12C68-5 protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and Write operations. The low voltage condition is detected
when V
CC
is less than V
SWITCH
. If the STK12C68-5 is in a Write
mode (both CE and WE are low) at power up after a RECALL or
after a STORE, the Write is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brown out conditions.
Noise Considerations
The STK12C68-5 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
CC
and V
SS,
using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK12C68-5 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage condi-
tions. When V
CAP SWITCH
, all externally initiated STORE
operations and SRAM Writes are inhibited. AutoStore can be
completely disabled by tying VCC to ground and applying +5V to
V
CAP
. This is the AutoStore Inhibit mode; in this mode, STOREs
are only initiated by explicit request using either the software
sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK12C68-5 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
Figure 5 and Figure 6 shows the relationship
between I
CC
and Read or Write cycle time. Worst case current
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK12C68-5
depends on the following items:
■ The duty cycle of chip enable
■ The overall cycle rate for accesses
■ The ratio of Reads to Writes
■ CMOS versus TTL input levels
■ The operating temperature
■ The V
CC
level
Preventing Store
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a V
OH
of at least 2.2V,
because it must overpower the internal pull down device. This
device drives HSB LOW for 20
μs at the onset of a STORE.
When the STK12C68-5 is connected for AutoStore operation
(system V
CC
connected to V
CC
and a 68
μF capacitor on V
CAP
)
and V
CC
crosses V
SWITCH
on the way down, the STK12C68-5
attempts to pull HSB LOW. If HSB does not actually get below
V
IL
, the part stops trying to pull HSB LOW and abort the STORE
attempt.
Figure 5. Current Versus Cycle Time (Read)
Figure 6. Current Versus Cycle Time (Write)
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