Cypress STK12C68-5 - Manual (Page 12)

STK12C68-5 (SMD5962-94599)
Document Number: 001-51026 Rev. ** Page 12 of 18
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
[18]
Parameter Alt Description
35 ns 55 ns
Unit
Min Max Min Max
t
RC
[14]
t
AVAV
STORE/RECALL Initiation Cycle Time 35 55 ns
t
SA
[17]
t
AVEL
Address Setup Time 0 0 ns
t
CW
[17] t
ELEH
Clock Pulse Width 25 30 ns
t
HACE
[17] t
ELAX
Address Hold Time 20 20 ns
t
RECALL
RECALL Duration 20 20
μs
Switching Waveform
Figure 13. CE Controlled Software STORE/RECALL Cycle
[18]
t
RC
t
RC
t
SA
t
SCE
t
HACE
t
STORE
/ t
RECALL
DATA VALID DATA VALID
6 # S S E R D D A 1 # S S E R D D A
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
Notes
17. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
18. The six consecutive addresses must be read in the order listed in
Table 1 on page 6. WE must be HIGH during all six consecutive cycles.
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