Welch Allyn Poem NIBP Module DeveloperS Kit Instructions - Installation Guide - Manual (Page 6)

POEM NIBP Module Developer’s Kit Instructions Welch Allyn OEM Technologies
Page 6 Confidential 810-1209-01 Rev. A
METHOD 2 - Logic-Level UART Connection From J4 to Host System
Configure JMPR3 and JMPR4 as shown in Figure 5. When used in this manner, the Interface
Board imposes no limitations on data rates.
Figure 5 - Logic-Level UART Serial Interface Connection
JMPR4 JMPR3
1 1
J6
J4
Configure JMPR3 and JMPR4 as shown.
Leave J6 unconnected.
1
7
9
23
2
6
12
24
Ground of host system
Data to host system
Data from host system
COMM_POL_SEL
Refer to the POEM NIBP
Module OEM
Implementation Manual
for details about
polarities, voltage levels,
and functionality.