Achronix Speedster22i Snapshot - Manual (Page 8)

Implementation
The ACX_SNAPSHOT macro is the top level module in the implementation of Snapshot. This
macro exists inside the Speedster Black-Box library file (for example: speedster_bb_synplify.v
for Synplify Pro users and speedster_bb_precision.v for Precision users) which must be
synthesized together with the user design (instantiation example shown below). User must
include the “speedster_bb*.v” file during synthesis while implementing the Snapshot macro.
Two clocks are present inside the Snapshot macro. These two clocks are
1. usr_clk: This clock is used for the user data in to the Snapshot macro
2. tck: This clock is used to read the data-out from Snapshot macro through the JTAG
tdo port. It is IEEE 1149.1 JTAG based TCK.
The usr_clk must match the desired clock frequency of the user’s design. Below is an
example how to implement the Snapshot macro inside the user’s design:
Example of Verilog Instantiation:
//////// Verilog Module for Top-Level Design Example with Snapshot Macro ///////
///////// as well as User’s Design block. This example will guide the user how //////
///////// to implement Snapshot macro with User’s Logic block. ////////////////////////////
module user_design_with_snap_shot (
input tck,
input trstn,
input tms,
input tdi,
output tdo,
input usr_clk
);
parameter MNTR_WIDTH = 72;
///// This above parameter should be varied (36, 72,108, 144) depending on user signals
///// to be monitored
wire [MNTR_WIDTH-1 :0] monitor_ch; /// Signals monitored in Snapshot
wire [35:0] trigger_ch; ///// Signals going to trigger-detector block to do pattern matching
wire rstn_out ; ///// Active low user reset signal.
wire Arm; ///// Indicates Snapshot activity.
wire [35:0] Stimuli; ///// User specified values for 3rd trigger pattern value
//////// Now Snapshot macro block instantiation ///////
ACX_SNAPSHOT #(.MNTR_WIDTH(MNTR_WIDTH))
snapshot_instance (
.tck(tck),
.tms(tms),
.trstn(trstn),
.tdi(tdi),
.tdo(tdo),
.usr_clk(usr_clk),
8 UG016, September 22, 2014