Achronix Speedster22i Snapshot - Manual (Page 5)

General Description and Architecture
The Snapshot macro samples user-signals in real time, and sends the captured data back
through the JTAG interface. The implementation supports the following features:
- Capture up to 144-bit wide data.
- Capture always 1024 samples of data at the user clock frequency
- Supports up to three separate 36-bit trigger conditions, each capable of operating on
any user signal. Each trigger condition supports “don’t care” feature (masking)
- All captured data will be read back serially with respect to TCK
Figure 2 shows the Snapshot architecture:
JTAP
Interface
Read-
Write
Control
Trigger
Detector
BRAM
Read/Write
Address
Counters
Registers
40
80-320
Trigger-Ch
User Clk
Monitor-Ch
Figure 2: Snapshot Block Diagram
The blocks comprising the Snapshot module are described in more detail in the following
sections.
JTAP Interface
The JTAG based tap controller, or JTAP, is a module auto-generated when Snapshot is used
in the design. It provides handshaking and connectivity between the Snapshot core in the
user logic and the JTAG interface.
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