Achronix Speedster22i Snapshot - Manual (Page 6)

Trigger Detector
As illustrated in Figure 3, the Trigger Detector receives one 36-bit each from the trigger
pattern (pattern_in), don’t care sequence (mask), and input data (channel_in). For every
channel_in sample, this block evaluates a corresponding match signal, called match_out. If
the corresponding mask bit is set high, match_out is asserted; otherwise, match_out remains
low, and is only asserted if the corresponding channel_in bit matches the pattern_in bit.
There is a sel_in pin which comes from a JTAG register for selecting between match_out
getting ORed or ANDed. If sel_in pin is asserted high match_out is ANDed or if sel_in pin is
asserted low match_out is ORed.
sel_in
pattern_in [35:0]
channel_in [35:0]
don’t_care [35:0]
usr_clk
match_out
Trigger Detector
Figure 3: Trigger Detector
Note: The 36bit trigger signals must always be the lowest 36 bits of the monitor signals
Read-Write Control Logic
The read-write control logic is essentially a set of state machines to interface with the
counters, the BRAM and the trigger detect circuitry to generate the appropriate signals for
proper storage of user data in the BRAM and for retrieval of this data to be displayed for the
user. It is the main interface between the JTAG circuitry in the rest of the modules in the
Snapshot macro and operates in the same domain as the user clock.
Counters and Registers
The read/write address counters are controlled through the read-write control logic, and
essentially ensure that captured data is appropriately written to and read from the BRAM.
There are also additional registers to monitor triggering mechanisms as well as for
implementation of the read-write control logic.
BRAM
The BRAM is the memory module used for storage of the captured data. It is a 80Kbit fully
featured true dual port (TDP) memory which acts as the buffering mechanism to supply the
captured data to the user through JTAG. More infotmation can be found on the BRAM in the
Speedster22iHD datasheet and the Speedster22iHD Macro Cell Library.
6 UG016, September 22, 2014