Achronix Speedster22i Snapshot User Manual

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JTAG Scan Chain: This option has several sub-options.

a. IR Bits Before Device: This option sets the number of instruction register bits before

the target FPGA device. Default value is ‘0’. (e.g. There are 23 IR-Bits in

Speedster/RadRunner. If the user has multiple Achronix FPGA devices being programmed on

the board through the JTAG Scan Chain, the user needs to specify this bit in the box. At the

end of this section this example will give an idea on how to set these values.)

b. IR Bits After Device: This sets the number of instruction register bits after the target

FPGA device. Default setting is ‘0’.

c. Target Device Offset in Scan Chain: It sets the cardinal number of the device in the

scan chain. Default is ‘0’.

Example: If the user has three Achronix FPGA devices already programmed via the JTAG

Scan Chain on the system, the user needs to implement the following in the Snapshot GUI:

Table 3: JTAG Scan Chain Example Implementation on the Snapshot GUI

Device Target Device Offset

in Scan Chain

IR Bits Before Device

IR Bits After Device

Trigger: The radio buttons to the left of the trigger groups allow the user to select the use of

1, 2, or 3 sequential triggers. If the radio button to the left of Trigger 1 is selected, Trigger 2,

and Trigger 3 are ignored. If the radio button to the left of Trigger 2 is selected, Trigger 3 is

ignored and Snapshot Debugger tool will trigger when Trigger 1 is matched, followed by a

match on Trigger 2. If the radio button next to Trigger 3 is selected, then Snapshot will trigger

after a match on Trigger 1, followed by Trigger2, followed by Trigger3.

a. Pattern: This trigger pattern specifies the 36-bit pattern of ‘1’s and ‘0’s to match on.

Each bit corresponds to one of the signals attached to monitor channels 0-35. The LSB

of this pattern bus connects to the monitor channel LSB, which is bit 0, and the MSB

of the pattern data will be connected to monitor channel MSB, which is bit 35. The

trigger pattern can be set either in HEX, or in BINARY.

b. Don’t Care: The Don’t Care bits specify which bits out of the trigger pattern are

ignored during a compare. If Don’t Care bit 3 is set to a ‘1’, then the signal attached to

monitor channel 3 will be ignored during trigger pattern compare. The Don’t Care

pattern can be set either in HEX, or in BINARY.

Monitor Channel Width: The Snapshot macro is parameterizable to channel widths of 72

and144 channels. The user must set the Monitor Channel Width to the value that corresponds

with the parameterized Snapshot RTL instantiation. Note that channels 0-71 are always

connected to the trigger mechanism. Once you have selected the Monitor Channel Width, the

signal names for each channel may be configured in the Monitor Channels table.

Pre-Store: This is an option which the user can set during the “Arm”ing of Snapshot. There

are four selections for this (0%, 25%, 50%, and 75%). When set to 0%, Snapshot macro begins

collecting samples once the trigger event is met. If set to 25%, 25% of the trace buffer depth is

filled with pre-trigger samples and the rest are post trigger samples. Similarly, when 50% is

selected, 50% of the trace buffer depth is filled with pre-trigger samples and the rest are post

trigger samples. 75% setting directs the Snapshot macro to collect 75% of the trace buffer

depth with pre-trigger samples and the rest are port trigger samples. Default setting is 0%.

UG016, September 22, 2014