Cypress Perform CY7C1393CV18 - Manual (Page 9)

CY7C1392CV18, CY7C1992CV18
CY7C1393CV18, CY7C1394CV18
Document #: 001-07162 Rev. *C Page 9 of 30
synchronized to the output clock of the DDR-II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in
Switching Characteristics on page 23.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary to reset the DLL
to lock it to the desired frequency. The DLL automatically locks
1024 clock cycles after a stable clock is presented. The DLL may
be disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device behaves in DDR-I mode (with one cycle
latency and a longer access time). For information refer to the
application note DLL Considerations in QDRII™/DDRII.
Application Example
Figure 1 shows four DDR-II SIO used in an application.
Figure 1. Application Example
LD
#
R/W
#
B
W
#
Vt = V REF
C C#
CQ
CQ#
K#
ZQ
Q
D
K C C# K
BUS
MASTER
(CPU
or
ASIC)
SRAM 1 SRAM 4
DATA IN
DATA OUT
Address
LD#
R/W#
BWS#
SRAM 1 Input CQ
SRAM 1 Input CQ#
SRAM 4 Input CQ
SRAM 4 Input CQ#
Source K
Source K#
Delayed K
Delayed K#
R = 50Ohms
R = 250Ohms
CQ
CQ#
K#
ZQ
Q
LD
#
R/W
#
B
W
S
# LD
#
R/W
#
Vt
Vt
Vt
R
R
R
A A
D
R = 250Ohms B
W
S
#
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